This application is based upon and claims the benefit of priority from Japanese patent application No. 2006-159312 filed on Jun. 8, 2006, the disclosure of which is incorporated herein in its entirety by reference.
The MTJ element used in the memory cell of the MRAM includes: a pinned magnetic layer whose magnetization is pinned in any direction; and a free magnetic layer whose magnetization can be varied by an external magnetic field. The pinned magnetic layer and the free magnetic layer are laminated such that a tunnel insulating film is sandwiched between them. In the MRAM, one-bit storage information is assigned to the relative magnetization state between the pinned magnetic layer and the free magnetic layer. For example, when the magnetizations of the pinned magnetic layer and the free magnetic layer are equal in direction, namely, in a parallel state, this case is defined as “0”. If the magnetizations of the pinned magnetic layer and the free magnetic layer are different from each other by 180 degrees, namely, in an anti-parallel state, this case is defined as “1”. Then, the reading from the MRAM is executed by using the fact that the MTJ resistance is different based on the magnetization state.
The writing principle of the typical MRAM will be described below. Write currents are supplied into a write word line extending in parallel to the magnetization easy axis of the magnetic layer and a write bit line extending vertically thereto, respectively. The magnetization of the free magnetic layer is switched in a desirable direction by the synthesis magnetic field generated by the respective write currents. In this way, the memory cell is selected and a writing operation is executed on the memory cell based on the magnetization switching property of the MTJ element. At this time, a lower limit and an upper limit exist in the write current value, and a writable margin is narrow. Thus, in order to selectively carry out the writ operation, a current value and a current waveform are required to be accurately controlled. Hence, a current source circuit becomes complex, which makes the high speed writing operation difficult.
The memory cell (2-Transistor-1-MTJ memory cell: 2T1MTJ cell) in which the write current is electrically selected by a transistor and a diode is disclosed in Japanese Laid-Open Patent Application JP-P2004-348934A (corresponding to U.S. Pat. No. 7,184,301(B2)). FIG. 1 is a view showing a part of a configuration of MRAM disclosed in Japanese Laid-Open Patent Application JP-P2004-348934A. The MRAM includes a memory array 101, a decoder 108 and a write circuit 109. Incidentally, on drawings in this Description, the MTJ element is indicated by the symbol of a variable resistor.
The memory array 101 includes: a plurality of word lines (WL) 103 extending in an X-direction; a plurality of first bit lines (/WBL) 104 extending in a Y-direction; a plurality of second bit lines (WBL) 105, a plurality of third bit lines (RBL) 110; and a plurality of memory cells 102 arranged in a matrix shape. In each of the plurality of word lines 103, one end is connected to a decoder 108. One first bit line 104, one second bit line 105 and one third bit line 110 provide one set of bit lines. The first bit line 104 and the second bit line 105 are complementary, and their one ends are connected to a write circuit 109. The third bit line 110 is connected to, for example, a reading circuit (not shown). Each of the plurality of memory cells 102 is arranged correspondingly to each of the intersections between the plurality of word lines 103 and the plurality of bit line sets.
The memory cell 102 includes a first transistor 106, a second transistor 116 and an MTJ element 107. In the first transistor 106, its gate is connected to the word line 103, and one terminal is connected to the first bit line 104, respectively. In the second transistor 116, its gate is connected to the word line 103, one terminal is connected to the other terminal of the first transistor 106, and the other terminal is connected to the second bit line 105, respectively. That is, the first transistor 106 and the second transistor 116 are connected in series between the first bit line 104 and the second bit line 105. In the MTJ element 107, one terminal is connected to the connection point between the first transistor 106 and the second transistor 116, and the other terminal is connected to the third bit line, respectively.
The decoder 108 selects the selection word line 103 from the plurality of word lines 103, at the times of the writing operation and the reading operation. The write circuit 109 supplies a write current IW in the direction corresponding to a write data, to the route of the first bit line 104, the selection cell 102 and the second bit line 105 in the selection bit line sets selected from the plurality of bit line sets based on an address signal, at the time of the writing operation. Here, the selection cell 102 is the memory cell 102 selected in the selection word line 103 and the selection bit line set from the plurality of memory cells 102.
In this invention, the circuit is devised such that the write current IW flows through only the selection memory cell 102. For example, the writing operation is carried out by the write current IW flowing from the second bit line 105 to the first bit line 104 in which both are complementary, at the time that the word line 103 is activated. This method has a merit that the selection property of the memory cell 102 at the time of the writing operation is dramatically improved. Thus, the current value and current waveform of the write current IW are not required to be accurately controlled, which can simplify the circuit, and it becomes easy to carry out the writing operation at a high speed.
In this way, in the 2T1MTJ, when the current value of the write current IW is greater than a magnetization switching threshold, the writing operation is stably executed. However, as the bit capacity of the memory array 101 is increased, a parasitic resistance 120 of the first bit line 104 and the second bit line 105 is increased. Thus, it is difficult to supply the write current IW having a sufficient value to the memory cell 102 located far away from the writing circuit 109. This is mainly caused by the following reasons.
In the writing operation, preferably, the write current IW that is as large as possible is supplied into the memory cell 102. The value of the write current IW is mainly limited by the on-resistances of the first transistor 106 and the second transistor 116 in the memory cell 102. Moreover, when the memory array 101 is large, it is also limited by the parasitic resistances 120 in the respective bit lines. At this time, the value of the write current IW is greatly limited by the parasitic resistance 120 on a termination side, as compared with the parasitic resistance 120 on a source side of the write current IW. For example, as shown in FIG. 1, when the write current IW is supplied from the second bit line 105 to the first bit line 104, as compared with the parasitic resistance 120 of the second bit line 105, the parasitic resistance 120 of the first bit line 104 greatly attenuates the value of the write current IW. This is because, since the source electrode voltage of the first transistor 106 is increased, the on-resistance of the first transistor 106 is increased, and the on-resistance of the second transistor 116 is also increased. Similarly, when the write current IW is supplied from the first bit line 104 to the second bit line 105, the parasitic resistance 120 of the second bit line 105 greatly decreases the value of the write current IW. That is, the on-resistances of the first transistor 106 and the second transistor 116 in the memory cell 102 are increased by the parasitic resistance 120 of the bit line on the side at which the write current IW terminates. This becomes the main reason that leads to the drop in the write current IW.
In order to avoid such a phenomenon, it is considered that the wiring widths of the first bit line 104 and the second bit line 105 are made thick, thereby decreasing the parasitic resistance 120, or the gate widths of the first transistor 106 and second transistor 116 in the memory cell 102 are made thick. However, all of those countermeasures result in the increase in the areas of the memory cell 102 and the memory array 101. Thus, the bit capacity of the memory array 101 cannot be efficiently increased. A technique is desired which can stably supply the sufficient write current IW to the memory cell without increasing the area of the memory array 101.
As the related art, Japanese Laid-Open Patent Application JP-P2001-307482A discloses a semiconductor storage device. This semiconductor storage device inputs and outputs a data through an input/output circuit coupled to an inner data line. This semiconductor storage device includes a DRAM array, a SRAM array, a data transferring means, a sense amplifier means and a control means. The DRAM array is composed of a plurality of dynamic memory cells arrayed in a matrix shape. The SRAM array is composed of a plurality of static memory cells arrayed in a matrix shape. The data transferring means is provided at a position different from the inner data line and transfers the data between the DRAM array and the SRAM array. The sense amplifier means detects, amplifies and latches the information of the memory cell selected in the DRAM array. The control means responds to the transferring instruction to the SRAM array from the DRAM array and activates the transferring means at a timing earlier than an activation timing of the sense amplifier means. The column line of the DRAM array is directly coupled to the data transferring means.
Japanese Laid-Open Patent Application JP-P2002-204271A discloses a termination circuit of a common bus and a common bus system. The termination circuit of this common bus is connected to a plurality of input/output units. The termination circuit of the common bus includes a signal input/output means, a waveform shaper means, a gate means, a connector means, a delaying means and an applying means. The signal input/output means captures the signal sent through the common bus and outputs the signal to the common bus. The waveform shaper means shapes the waveform of the signal on the common bus captured through this signal input/output means. The gate means captures the output signal from this waveform shaper means, and controls whether this signal is stopped or outputted from an own output end in accordance with a control signal. The connector means connects the output end of this gate means to an input end linked to the output end of the signal input/output unit connected to the common bus. The delaying means captures and delays the output of the waveform shaper means. The applying means applies the output of an exclusive OR between this delaying means output and the waveform shaper means output as the control signal of the gate means.
Japanese Laid-Open Patent Application JP-P2004-227754A (corresponding to U.S. Pat. No. 6,839,270(B2)) discloses a system for and a method of accessing a 4-conductor magnetic random access memory. This control circuit is intended to perform the writing/reading operation from/to a magnetic random access memory (MRAM) cell. This control circuit includes: a row decoder (608), a first reading/writing row driver (609), a plurality of global row write conductors, a plurality of row taps, and a second reading/writing row driver (610). The first reading/writing row driver (609) is connected to the row decoder (608). The plurality of global row write conductors is connected to the first reading/writing row driver (609). The plurality of row taps is connected to the plurality of global row write conductors, respectively. The second reading/writing row driver (610) is connected to the global row write conductor.